Hardware logic emulation systems and acceleration systems are used for functional verification of integrated circuit designs. A logic emulator is typically used with the testing environment provided through an in-circuit connection to other hardware, while an accelerator is typically used with or like a software simulator, with the testing environment provided through software testbenches or test vectors. Often the same core machine is used in either application. Hardware logic emulators and accelerators are known devices that implement a user's design in a plurality of programmable integrated circuits. Such logic emulators and accelerators are available from various vendors, including Cadence Design Systems, Inc., San Jose, Calif., United States of America, and others. Typical systems utilize either programmable logic chips, which are programmably interconnected or a system of special-purpose processor chips.
In programmable logic chip (e.g., field programmable gate array, or FPGA) based systems, the logic contained in the user's design (referred to herein as the “design under verification”, or “DUV”) is modeled directly in programmable logic form. Examples of hardware logic emulation systems using programmable logic devices can be seen in, e.g., U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191. U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191 are incorporated herein by reference. FPGA based emulators and accelerators require FPGA placement and routing, may suffer from timing-induced errors, can present difficult modeling problems for complex memories, and suffer from low performance due to insufficient FPGA package pins.
In processor-based emulation and acceleration systems, the user's design is processed so that its functionality appears to be created in the processors by calculating the outputs of the design. The logic itself is not implemented in a processor-based emulation system, meaning that the DUV does not take actual operating form in the processors. Exemplary processor-based accelerators have been built in large-scale multi-million-gate ASIC-based implementations. These machines are very powerful, but can be too large and expensive for many designs. Further, due to their ASIC implementation of the processor modules, such machines cannot allow macro-level function processors, general-purpose (CPU-based) processors and other specialized functions since the required mix among different types varies widely from design to design. Examples of hardware logic emulation and acceleration systems using processor chips can be seen in, e.g., U.S. Pat. Nos. 4,306,286, 4,656,580, 4,914,612, 5,551,013, 6,035,117, 6,051,030. U.S. Pat. Nos. 4,306,286, 4,656,580, 4,914,612, 5,551,013, 6,035,117, 6,051,030 are incorporated herein by reference.
In processor based acceleration or emulation systems, massively parallel multiprocessors are used for accelerating the simulation of or emulating logic designs. Frequently, these logic designs are expressed at the register-transfer-level and are not limited to gate-level Boolean logic. These designs also include macro operations such as multi-bit addition, multiplication and selection. Accelerated logic simulation is needed since software logic simulation, the most common form of functional verification, is not fast enough to execute software or process large datasets on designs with 500K gates and above. For example, prior event-based gate-level simulation accelerators such as NSim operate at the gate level with full timing simulation, which prevents enough performance to be meaningful.
Thus, there is a need for a design verification system that can flexibly implement various different types of processors depending upon the design being verified.